Testing the LABS modules

In the previous post in this series I introduced the LABS problem, and explained some of the relevant properties of the binary sequences. I also sketched out my proposed solution and started work on implementing this solution in SystemVerilog.

In this post I will cover some design verification for the modules we have designed thus far, so that we can be confident of our basic building blocks when we start wiring them together.

Searching for Low Autocorrelation Binary Sequences

In this post we will take a look at a numerical optimisation problem and how we might implement it on an FPGA. The problem in question is the search for binary sequences with low autorrelation values (Low-Autocorrelation Binary Sequences, or LABS for short). These sequences have applications in communications engineering, mathematics and statistical physics.

Zynq 7000: Adding Custom Blocks

In the previous posts we have build our designs using just the built-in IP blocks provided by Xilinx inside Vivado. At some point you will likely want to add more specialized behaviour using bespoke HDL code. In this blog post I will explain how to add custom modules to a Vivado block design. The functionality in this design will mirror that of this previous post, where we made an LED blink at a constant rate.

Zynq 7000: Using a Command Line Workflow

So far we have used the graphical workflow to create block designs inside Xilinx Vivado. In this post I will present a different workflow based on TCL scripts, which can be run from the command line. Using TCL scripts a number of advantages when it comes it sharing designs across computers, with collaborators and when storing them in VCS (such as git). It also makes it easier to re-use (parts of) block designs in different projects.

Using the ARM cores on the Xilinx Zynq 7000

In this post we will build on our first experience with the Xilinx tools and learn how to use the ARM cores to interact with the programmable logic. This is the second post in the Zynq 7000 seminar series; in this post I will show how to achieve communication between the programmable logic (PL) and processing system (PS) sides of the Zynq 7000.

Getting started with the Xilinx Zynq 7000

The Xilinx Zynq 7000 series systems-on-chip (SoC) combine an FPGA with ARM Cortex-A9 microprocessor cores, providing buses for transferring data between the two parts of the SoC. These devices are excellent for data acquisition tasks: the FPGA can be used to interface with high-speed data convertors such as ADCs and DACs, and to apply computationally intensive data processing tasks to the data. The processed, and potentially downsampled, data can then be transferred to the ARM core(s) for further processing.